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Fault-tolerance Carbon Nanotube-based Computer Logic Design

Jie Chen*, Joe Mundy, Iris Bahar, and J. M. Xu

Division of Engineering, Brown University,
Providence, RI 02912 USA

This is an abstract for a presentation given at the
11th Foresight Conference on Molecular Nanotechnology

 

Nanoscale devices, whether assembled lithographically3 or self-assembled chemically1,2,6, will have a high probability of failure. Therefore, any architecture built from large numbers of nanoscale devices will necessarily contain a large number of defects, which fluctuate on time scales comparable to the computation cycle. The challenge for engineers is to develop an architecture that is dynamically defect tolerant.

In this paper, we propose fault-tolerance Y-junction nanotube-based computer devices and architectures. These Y-junction nano-scale devices have been proven to possess good transistor behavior and they can be synthesized by chemical vapor deposition 4,5. We use DNA molecules to help alleviate the problems of Y-junction nanotube wiring and positioning at the nanometer scale because of DNA's self-assembly and molecular recognition abilities. To circumvent the DNA conductivity problem, we substitute the imino proton of each base pair with a metal ion (Zn2+) to alter DNA electronic properties, which controllably converts the normal DNA into Metallic-DNA. In addition, we propose a probabilistic-based design methodology for designing nano-scale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of Gibbs energy that depends on neighboring nodes in the network. We expect that this relationship will provide an important bridge between physics and computation. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm7. Finally, we will illustrate the proposed design methodology with some elementary logic examples.

References:

1. P.G. Collier, A. Zettl, A. T. H. Bando, and R. E. Smalley, Nonotube nanodevice. Science, 278: 100-102, 1998

2. S. J. Tans, A. R. M. Verschueren, and C. Dekker. Room-temperature transistor based on a single carbon nanotube, Nature, 393:49-51, 1998

3. Lim, Jung-Hyurk; Mirkin, Chad A. "Electrostatically Driven Dip-Pen Nanolithography of Conducting Polymers," Adv. Mat., 2002, 14(20), 1474-1477.

4. J.Li, C.Papadopoulos, J.M. Xu, and M.Moskovits, "Highly-ordered carbon nanotube arrays for electronics applications". Applied Physics Letters, 75(3):367--, July 1999.

5. R.Martel, V.Derycke, J.Appenzeller, S.Wind, and P.Avouris. "Carbon nanotube field-effect transistors and logic circuits.", Proceedings of the 39th Conference on Design Automation

6. T.W. Odom, J.-L. Huang, P. Kim and C.M. Lieber, "Structure and Electronic Properties of Carbon Nanotubes" J. Phys. Chem. B 104, 2794-2809 (2000)

7. J. Chen, J. Mundy, and I. R. Bahar. "Probabilistic Approaches to Nano Computation". IEEE Trans. on Computers

Abstract in Microsoft Word® format 22,342 bytes


*Corresponding Address:
Jie Chen
Division of Engineering, Brown University
182 Hope Street
Providence, RI 02912 USA
Phone: (401) 863-1455 Fax: (401) 863-9039
Email: Jie_Chen@Brown.Edu
Web: http://binary.engin.brown.edu



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