Self-assembled nano-particles as electronic devices
of Electrical Engineering, Cornell
University, Ithaca, New York 14853
This is an abstract
for a presentation given at the
Foresight Conference on Molecular Nanotechnology.
There will be a link from here to the full article when it is
available on the web.
Self-assembed nanostructures have raised great research interests in theoretical understanding (Ledentsov et al 1996; Tiwari et al 1996; Tersoff and Tromp 1993) and practical applications (Ledentsov et al 1996; Yano et al 1993; Welser et al 1997) in integrated circuit technology. Due to carrier confinement in the small geomtry, energy levels are quantized and much work has been devoted to study this type of quantum dots (QDs) (Ledentsov et al 1996, Tiwari et al 1996). Since these QDs are formulated by self-assembled process, they are usually arranged in ordered arrays. No interconnect structure that is definable by designers can be used to directly sample the information stored. In this paper, we will propose a new type of electron devices, multi-floating-gate EEPROM, which contains lithographically defined sensing structures around the self-assembled QDs. A possible layout of NXN floating gates is shown below.
There is an N X N self-assembled QD array circumscribed by the analog sensing structure defined by the conventional VLSI lithography, which will serve as the address and data lines (in analog or collective fashion) for the basic module. The cross section shows the EEPROM-like layer structure with QD sitting on a thin tunneling oxide and a writing gate on top of the second oxide. The self-assembled process step can be performed before and after the lithography steps, depending on the relative thermal budget of each step. If the self-assembled process is done before lithography, the position of the QD array within the sensing structure cannot be well controlled and is subject to the resolution of lithography. However, since QD will self organize to a periodic array, the sensing structure formed selectively will likely contain the same number of QD across the die. If the self-assembled process step is performed after lithography of the sensing structure, the array of QD may be self-positioned too, since formation of QD to minimize the surface free energy may be constrained by the underlying structure.
Two potential electronic device applications of the above module are considered. First, the structure can be used as a multi-bit EEPROM cell. Sensing and addressing of the individual QD will be accomplished by voltage and current characteristics of the four corner contacts and the MOS channel under the QD array, which is determined by the Coulomb interactions between QD and the analog interface. Since the electronic states in QD may be quantized owing to the confinement, it is probably easier to differentiate multi-levels in one QD than the conventional EEPROM cell without the quantum confinement effects. To achieve room-temperature operations, this may place an upper limit on $N$ for sensibility and addressability. Nevertheless, the interface analog circuit will be connected with amplifiers with thermal compensation on the word and bit lines. Charging of the floating QD can be achieved by applying a large bias on the writing gate. Since the tunneling efficiency is a strong function of the oxide electric field and the QD capacitance is very small (i.e., a small charge on the floating QD will cause a significant potential perturbation.) For extremely small capacitance, single electron charging can be observed, addressability during charging/writing should be comparable to the sensing/reading case. Charge leakage out of QD will be negligible when the bias of the writing gate is removed, which is similar to the conventional EEPROM case. Quantization caused by Coulomb blockade effect actually helps retain the discrete electrons in QD.
As a simple illustrative example, a 2 X 2 QD array with corner sensing and addressing elements as diagonal EEPROM source/drain pairs is shown below. For convenience, it is assumed that when none of the QD is charged, both diagonal source/drain pair will have a high conductance (inverted channel under the write-gate exists). When the corner dot close to source a (b) is charged, the conductance between source a and drain a will be significantly reduced, while the conductance between source b and drain b will remains high. When the corner dot close to drain a (c) is charged, the conductance between source a and drain a will be reduced, but not as much as the case in (b) if the sensing voltage applied to drain a is not too small. This unsymmetrical conductance behavior is due to the nonlinear IV characteristics of split-gate MOSFET, which has actually been used to implement multiple-step logic (Karasawa 1993). When both corners along the diagonal of source a and drain a are charged, the conduction between source a and drain a should basically shut off. The four conductance states in each diagonal sensing pair will be used to differentiate the 16 possible binary states in the 4 QDs. Remember that the bit-line sense amplifiers are shared by many modules. Hence, a sophisticated design will not introduce heavy area penalty. A very similar argument can be applied to the 3 X 3 QD array and used as the storage of 8 bits (the center dot is not used). This will also require the bit-line sense amplifiers to distinguish among 8 possible conduction states. On the other hand, if the bit-line sense amplifier can distinguish even more conduction levels, the quantization of charged states in each QD can be utilized to store further more information in this basic module. The four corner contacts can also be used to create necessary electric field profiles during the write operation with a large voltage applied on the writing gate.
An illustrative example showing how multiple-QD floating gate EEPROM can be sensed. The charged QD is represented by dark circles. The diagonal lines represent possible current levels (solid lines: highest conduction, dashed lines: medium conduction, and dotted lines: low conduction.
Preliminary quantitative studies have been performed on the split-gate depletion-type MOSFETs. These simulation results show that conduction modulation described above is valid. The gate length for the device under study is 200nm, gate separation 200nm and gate oxide thickness is 6nm.
The potential and concentration under different bias conditions are shown below.
The IV characteristics under various bias conditions are shown below.
If all X dimension is shrunk 4 times and Y dimension shrunk 4 times for the previous device, we still have enough resolution in IV characteristics.
The second potential application of the previous structure will be array of FGMOS (floating-gate MOS) synapses (Diorio et al 1996) for analog long-term learning circuitry. The memory storage in QD is nonvolatile, and hot-electron injection and electron tunneling into the quantized states of QD allow bi-directional memory updates. Since these updates strongly depends on both the stored charge in QD and the channel current below the QD layer, the array of synapses can implement various learning functions. Rules of learning can be derived from the injection and tunneling processes. This is different from the EEPROM function above, since the synapse cell permits simultaneous memory reading and writing. Array of synapse transistors can compute the array output and individual QD memory updates in parallel.
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Edwin C. Kan
404 Phillips Hall, Cornell University, Ithaca, NY 14853
Phone: (607) 255-3998; Fax: (607) 255-4777
Email: firstname.lastname@example.org; Web: http://www.ee.cornell.edu/~kan.