Hardware description languages, such as VHDL and Verilog, are standard tools in the design of electronic circuitry, and are virtually indispensable for the development of complex VLSI devices. These languages provide a formal framework for design and simulation at various levels of abstraction. A design represented in, say, Verilog, can be checked against design rules (e.g. for fanout), simulated for logic, simulated for timing, simulated for power consumption or heat generation, and/or automatically placed and routed into masks for chip production.
There are major efforts at high-level system description languages for other design tasks, such as UML for business software systems. However, the design of physical mechanisms has to date proved largely resistant to this approach. A primary reason for this discrepancy is that there is in digital electronics the closed Boolean behavioral model which forms a natural abstraction level for specification, whereas such a level is much more difficult to find for physical machinery. Other contributing reasons include the fact that the visual and spatial intuitions of mechanical engineers play a much larger role in their constructions than do those of logic designers; the visual nature of CAD systems has developed to reflect this fact.
Two trends, however, place mechanical design in increasing need of high-level description languages. First is the increasing complexity of buildable systems. MEMS promises systems with on the order of a million parts; molecular machine systems could exceed a billion. Such systems, no less than a millions-of-devices microprocessor, will require formal high-level design and simulation tools.
Second is the increasing use of digital logic in controllers, creating machines that are not so much electromechanical as "logicomechanical". The spectacular failure of such major hardware-and-software projects as the Denver International Airport baggage-handling system shows the need for new techniques as such systems increase in complexity.
This paper describes Caslor, a prototype experimental hardware and software description language for logicomechanical systems. Caslor is experimental in that it remains to be seen which levels of abstraction are appropriate for such a language. Caslor consists, like Verilog, of a module-defining facility, where each module can be defined in terms of an arrangement of other modules, or described behaviorally in a programming language. In Verilog, the language is C-like; Caslor's language is higher-level but still general-purpose. The intent is to provide a facility to simulate embedded controllers.
As in VHDL, it is possible to describe or not describe various aspects of the behavior of a module, including in Caslor's case shape, position, velocity, force, energy, and so forth. This allows for experiments with various combinations to determine which, if any, are useful in a high-level system description.
J. Storrs Hall, PhD.
Institute for Molecular Manufacturing
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