This paper describes original development efforts that are currently underway for the design, simulation, and development of nanotechnology-based molecular test equipment (MTE). This is part of a research effort for testing integrated circuits independent of traditional automatic test equipment (ATE) through the fabrication of MTE within integrated circuits (ICs). The proposed technology is anticipated to provide a means of fast, accurate, and inexpensive identification of failed integrated circuits (ICs) on electronic circuit boards, resulting in potential savings in the order of billions of dollars in development and recurring support costs over the product life cycle. This is accomplished through the use of a combination of molecular test equipment, nanoprobes, and electrochemical failure indicators. The molecular test equipment is fabricated and embedded within the individual integrated circuit in the chip substrate. Nanoprobes containing molecular test equipment connect between the surface and the substrate of the integrated circuit at various functional areas. An electrochemical indicator placed on the surface of the chip receives signals from the molecular test equipment and nanoprobes, initiating a chemical reaction that provides a visual indication to a technician that the integrated circuit is faulty.
In our development process IC device simulation is performed to assess the electrical, chemical, and structural properties of integrated and adjacent substrate devices. Through this approach the nominal and failed device performance parameters of interest to substrate- based MTE are ascertained. Definition of these properties is the first step towards determining MTE functional and operational requirements, and designing effective means to fulfill these requirements.
Discussion of the development and application of MTE within IC architectures will be provided, including such topics as the effect of substrate composition on the design and implementation of MTE, interfaces between MTE and IC devices, and reporting of MTE results to the IC surface and technician. Potential application areas within different device functions will also be identified. Equivalent circuit diagrams will be provided to illustrate the differences between existing circuit device configurations and MTE-augmented devices.
This paper will conclude by describing the advantages of modeling and simulation in the performance of the research, and its contribution to the project as a whole with respect to cost and schedule reduction and risk mitigation prior to fabrication. The feasibility of the approach will be discussed based on current and anticipated future technology capabilities in the context of design and prototype development of key elements of MTE.