The International Technology Roadmap for Semiconductors includes “bottom up” as a next step within a “top down” roadmap as Moore’s Law advances further into the nanoscale realm. The following business news from EE Times is brought to our attention by Dr. Rob Meagley, who was a mentor to work in this area at Intel and later at UWI NSEC. Rob is now an informal advisor to Foresight. From “IBM, JSR roll out self-assembly litho“:
JSR Corp., along with its U.S. operations, JSR Micro Inc., have rolled out a new directed self-assembly (DSA) technology for the sub-20-nm half-pitch node.
Developed as part of an ongoing research agreement with IBM Corp., the new technology eliminates dual exposure steps and is compatible with conventional 193-nm lithography equipment.
At SPIE last year, more than 10 papers on the conference schedule focused on directed self-assembly, a technology that combines lithographically defined substrates and self-assembled polymers. Research has focused on using lithography to alter the surface of a silicon wafer, then adding block co-polymers that assemble themselves into regular arrays along the defined pattern.
Directed self-assembly first landed on the ITRS in 2007 as a potential solution for leading-edge, critical layer lithography. The technology is still part of the ITRS as of the 2009 edition.
Still in the R&D stage, DSA is aimed for a range of devices, such as cylindrical patterns, vertical cylindrical patterns, nanowire arrays, FinFETs, among others, according to a paper from IBM at SPIE here.
One of the first applications appears to be the fabrication of a replicator in nano-imprint lithography. With a DSA-enable replicator, nano-imprint can be used for bit-pattern media applications in disk drives, according to IBM. …
Further details can be found on the Next Big Future web site “Directed self-assembly (DSA) technology for the sub-20-nm half-pitch nodes from JSR and IBM“.